A direct conversion receiver (DCR) is a type of radio receiver that does not use an intermediate frequency (IF). DCRs and digital very low IF receivers (DVLIF) are becoming common in cellular telephone handsets. A common problem with DCRs is that different components of the receiver may cause a DC offset voltage to be added to a received input signal. The DC offset voltage affects the operation of the receiver in a manner similar to interference. However, unlike interference, the DC offset voltage is generated internally to the receiver.
FIG. 1 illustrates, in block diagram form, a receiver 10 in accordance with the prior art. Receiver 10 includes a low IF front end 12 and a base band receiver 14. Front end 12 includes a low noise amplifier 16, a coupler 18, a mixer 20, a divider 22, and a frequency synthesiser 24. Baseband receiver 14 includes amplifier 30, active low pass filter 32, baseband sigma delta modulator 34, decimation filter 36, digital quad mixers 38, digital filter 40, digital integrator 42, and digital-to-analog converter (DAC) 44.
Each of the components of front end 12 may contribute to the DC offset voltage. For example, leakage from frequency synthesiser 24 may leak back into front end 12 through the antenna and may be mixed back into the signal path via mixer 20. Also, changing the gain of low noise amplifier 16 may change the level of leakage and DC offset.
Prior art receiver 10 uses a feedback path to reduce the DC offset. The feedback path starts at the output of digital filter 40 and feeds back into the signal path at the input of amplifier 30 via DAC 44. This type of feedback path is known as a mixed mode approach, where a digital signal is converted to an analog signal and provided at the input of base band receiver 14. A problem with this approach is that it requires a relatively long period of time to remove the DC offset because of the number of components in the feedback path that contribute to the delay.
Typically, in a cellular telephone system the DC offset is removed during a time period that is prior to the time period used for processing the input signals. In some applications, such as for example, Global System Mobile (GSM), the receiver may need to be powered up from standby mode as early as 400 microseconds prior to processing the received signals in order have enough time to reduce the DC offset. This significantly reduces standby time and increases power consumption.
European Patent Application EP-A-0 709 970 (General Electric Company) describes a DC correction arrangement for an analog-to-signal converter (ADC). The arrangement uses a single bit quantizer and has an accumulator in the feedback correction path.
United Kingdom Patent Application GB-A-2 328 353 (NEC) describes a correction system for use with a baseband receiver having two channels. A feedback signal for the DC offset estimation is provided at a second filter.
Therefore, a need exists for performing DC offset correction in a DCR or a DVLIF receiver that requires a shorter DC adapt period.